Shih-Hao Wang

RTL Design and Front-end Flow Implementation ● Designed mixed-signal block-level IPs (crystal oscillator controller, OTP controller) and established comprehensive testbenches to ensure strict compliance with design specifications. ● Collaborated with analog designers to define interface specifications and identify critical corner cases, ensuring design robustness and preventing potential functional failures. ● Executed the front-end design flow, including synthesis, STA, LEC, CDC, and Lint, to ensure timing closure, functional equivalence, cross-domain signal integrity, and high-quality RTL code. ● Performed Gate-Level Simulation (GLS) with SDF back-annotation to verify functional integrity and timing closure of the post-synthesis netlist. ● Authored comprehensive design documentation for digital IP , including functional overview, block diagrams, and simulation waveform analysis, to support design verification and cross-functional knowledge transfer. DFT & MBIST Development ● Optimized scan insertion and ATPG flows to generate high-quality test patterns, successfully boosting test coverage from 94% to 99%. ● Executed the Tessent MBIST flow and integrated memory block IPs in accordance with the memory group architecture defined in design specifications. ● Performed ATPG pattern GLS and resolved critical mismatch and zero-delay oscillation issues, ensuring pattern integrity and accurate test results. ● Analyzed ICL files to understand the DFT instrument connectivity architecture, and customized PDL scripts to generate targeted test patterns with specific test sequences, enhancing test flexibility for targeted validation scenarios.