{"canonicalUrl":"https://humetric.net/p/profile-fb0700b977c44da59c60f9c9ae8f0390","profileVersion":"d17c0265-2534-4eaf-9582-8ba2a9dae3af","lastUpdated":"2026-10-19T14:45:37.432201+00:00","profile":{"display_name":"Shih-Hao Wang","last_updated":"2026-10-19","slug":"profile-d8255366772a43ac","summary":"RTL Design and Front-end Flow Implementation\n● Designed mixed-signal block-level IPs (crystal oscillator controller, OTP controller) and established comprehensive testbenches to ensure strict compliance with design specifications.\n● Collaborated with analog designers to define interface specifications and identify critical corner cases, ensuring design robustness and preventing potential functional failures.\n● Executed the front-end design flow, including synthesis, STA, LEC, CDC, and Lint, to ensure timing closure, functional equivalence, cross-domain signal integrity, and high-quality RTL code.\n● Performed Gate-Level Simulation (GLS) with SDF back-annotation to verify functional integrity and timing closure of the post-synthesis netlist.\n● Authored comprehensive design documentation for digital IP , including functional overview, block diagrams, and simulation waveform analysis, to support design verification and cross-functional knowledge transfer.\n\nDFT & MBIST Development\n● Optimized scan insertion and ATPG flows to generate high-quality test patterns, successfully boosting test coverage from 94% to 99%.\n● Executed the Tessent MBIST flow and integrated memory block IPs in accordance with the memory group architecture defined in design specifications.\n● Performed ATPG pattern GLS and resolved critical mismatch and zero-delay oscillation issues, ensuring pattern integrity and accurate test results.\n● Analyzed ICL files to understand the DFT instrument connectivity architecture, and customized PDL scripts to generate targeted test patterns with specific test sequences, enhancing test flexibility for targeted validation scenarios.","years_experience":2,"skills":["Design Compiler","DFT Compiler","spyglass","SystemVerilog","tessent","TestMAX ATPG","verdi","Verilog","Xcelium"],"experiences":[{"id":"09a46e[contact removed]-b090-010fd424b08b","person_id":"ccf84d0a-8482-4b11-bad5-485eefedc2d2","title":"Digital IC design engineer","company":null,"start_date":"2024/01","end_date":"now","description":"RTL Design and Front-end Flow Implementation\n● Designed mixed-signal block-level IPs (crystal oscillator controller, OTP controller) and established comprehensive testbenches to ensure strict compliance with design specifications.\n● Collaborated with analog designers to define interface specifications and identify critical corner cases, ensuring design robustness and preventing potential functional failures.\n● Executed the front-end design flow, including synthesis, STA, LEC, CDC, and Lint, to ensure timing closure, functional equivalence, cross-domain signal integrity, and high-quality RTL code.\n● Performed Gate-Level Simulation (GLS) with SDF back-annotation to verify functional integrity and timing closure of the post-synthesis netlist.\n● Authored comprehensive design documentation for digital IP , including functional overview, block diagrams, and simulation waveform analysis, to support design verification and cross-functional knowledge transfer.\n\nDFT & MBIST Development\n● Optimized scan insertion and ATPG flows to generate high-quality test patterns, successfully boosting test coverage from 94% to 99%.\n● Executed the Tessent MBIST flow and integrated memory block IPs in accordance with the memory group architecture defined in design specifications.\n● Performed ATPG pattern GLS and resolved critical mismatch and zero-delay oscillation issues, ensuring pattern integrity and accurate test results.\n● Analyzed ICL files to understand the DFT instrument connectivity architecture, and customized PDL scripts to generate targeted test patterns with specific test sequences, enhancing test flexibility for targeted validation scenarios.","position":0}],"educations":[{"id":"d9b73695-8e58-47ea-afdf-3f958a1e18cc","person_id":"ccf84d0a-8482-4b11-bad5-485eefedc2d2","school":"National Cheng Kung University","degree":"Master","field":"Electrical Engineering","start_year":2021,"end_year":2024}],"projects":[{"id":"7387aaef-fe7f-43cf-864b-6885fbc2cb19","person_id":"ccf84d0a-8482-4b11-bad5-485eefedc2d2","name":"Digital IC Design","description":"Implemented an edge-based line average interpolation algorithm in Verilog for image processing, transforming interlaced images into non-interlaced formats. Developed a median filter engine in Verilog, implementing boundary handling techniques to maintain consistent image dimensions during processing.","url":null,"technologies":["Verilog"],"position":0}]},"chunksVersion":"profile-chunks-v4","approvedDiscoveryQueries":[],"evidence":[{"id":"identity:0","type":"identity","ordinal":0,"locale":"en","text":"Shih-Hao Wang. 2 years experience","fieldKeys":["display_name","years_experience"]},{"id":"summary:0","type":"summary","ordinal":0,"locale":"en","text":"Shih-Hao Wang. Summary / 簡介: RTL Design and Front-end Flow Implementation\n● Designed mixed-signal block-level IPs (crystal oscillator controller, OTP controller) and established comprehensive testbenches to ensure strict compliance with design specifications.\n● Collaborated with analog designers to define interface specifications and identify critical corner cases, ensuring design robustness and preventing potential functional failures.\n● Executed the front-end design flow, including synthesis, STA, LEC, CDC, and Lint, to ensure timing closure, functional equivalence, cross-domain signal integrity, and high-quality RTL code.\n● Performed Gate-Level Simulation (GLS) with SDF back-annotation to verify functional integrity and timing closure of the post-synthesis netlist.\n● Authored comprehensive design documentation for digital IP , including functional overview, block diagrams, and simulation waveform analysis, to support design verification and cross-functional knowledge transfer.\n\nDFT & MBIST Development\n● Optimized scan insertion and ATPG flows to generate high-quality test patterns, successfully boosting test coverage from 94% to 99%.\n● Executed the Tessent MBIST flow and integrated memory block IPs in accordance with the memory group architecture defined in design specifications.\n● Performed ATPG pattern GLS and resolved critical mismatch and zero-delay oscillation issues, ensuring pattern integrity and accurate test results.\n● Analyzed ICL files to understand the DFT instrument connectivity architecture, and customized PDL scripts to generate targeted test patterns with specific test sequences, enhancing test flexibility for targeted validation scenarios.","fieldKeys":["summary"]},{"id":"skills:0","type":"skills","ordinal":0,"locale":"en","text":"Shih-Hao Wang. Skills / 技能: Design Compiler, DFT Compiler, spyglass, SystemVerilog, tessent, TestMAX ATPG, verdi, Verilog, Xcelium","fieldKeys":["skills"]},{"id":"discovery:0","type":"discovery","ordinal":0,"locale":"en","text":"Shih-Hao Wang. Experience / 年資: 2 years experience. Expertise / 專長: Design Compiler, DFT Compiler, spyglass, SystemVerilog, tessent, TestMAX ATPG, verdi, Verilog, Xcelium","fieldKeys":["display_name","years_experience","skills"]},{"id":"experience:0","type":"experience","ordinal":0,"locale":"en","text":"Shih-Hao Wang. Experience / 經歷: Digital IC design engineer. 2024/01 to now. RTL Design and Front-end Flow Implementation\n● Designed mixed-signal block-level IPs (crystal oscillator controller, OTP controller) and established comprehensive testbenches to ensure strict compliance with design specifications.\n● Collaborated with analog designers to define interface specifications and identify critical corner cases, ensuring design robustness and preventing potential functional failures.\n● Executed the front-end design flow, including synthesis, STA, LEC, CDC, and Lint, to ensure timing closure, functional equivalence, cross-domain signal integrity, and high-quality RTL code.\n● Performed Gate-Level Simulation (GLS) with SDF back-annotation to verify functional integrity and timing closure of the post-synthesis netlist.\n● Authored comprehensive design documentation for digital IP , including functional overview, block diagrams, and simulation waveform analysis, to support design verification and cross-functional knowledge transfer.\n\nDFT & MBIST Development\n● Optimized scan insertion and ATPG flows to generate high-quality test patterns, successfully boosting test coverage from 94% to 99%.\n● Executed the Tessent MBIST flow and integrated memory block IPs in accordance with the memory group architecture defined in design specifications.\n● Performed ATPG pattern GLS and resolved critical mismatch and zero-delay oscillation issues, ensuring pattern integrity and accurate test results.\n● Analyzed ICL files to understand the DFT instrument connectivity architecture, and customized PDL scripts to generate targeted test patterns with specific test sequences, enhancing test flexibility for targeted validation scenarios.","fieldKeys":["experiences"]},{"id":"education:0","type":"education","ordinal":0,"locale":"en","text":"Shih-Hao Wang. Education / 學歷: Master. Electrical Engineering. National Cheng Kung University","fieldKeys":["educations"]},{"id":"project:0","type":"project","ordinal":0,"locale":"en","text":"Shih-Hao Wang. Project / 專案: Digital IC Design. Built with / 使用技術: Verilog. Implemented an edge-based line average interpolation algorithm in Verilog for image processing, transforming interlaced images into non-interlaced formats. Developed a median filter engine in Verilog, implementing boundary handling techniques to maintain consistent image dimensions during processing.","fieldKeys":["projects"]}]}