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A semiconductor research master's student with project experience in RTL verification, DFT, ASIC physical implementation, FPGA acceleration, and hardware-software co-design. Research focuses on hardware acceleration for fully homomorphic encryption-based deep learning, including FHE-friendly neural networks, algorithm-hardware co-design, and high-throughput architectures for kernels such as NTT.
Skills
Experience
Teaching Assistant, Integrated Circuit Design Lab — National Tsing Hua University
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Mentored 75 students in RTL design and debugging; developed a Transformer-model reference design and explained topics including clock gating and synthesis.
Featured projects
SiCADA 600 - SoC Design & Verification Course Project
AHB-Lite · DMA · APB · Clock-Domain Crossing · Asynchronous FIFO · SEC-DED ECC · UVM · SystemVerilog
Integrated a dual-clock AHB-Lite DMA subsystem with packet reception, APB-programmable control, asynchronous FIFO/metadata CDC, and SEC-DED ECC; passed 68 end-to-end packets with 0 scoreboard mismatches. Built course-project UVM testbenches with sequencers, drivers, monitors, scoreboards, and functional coverage. Used instructor-approved GenAI for implementation/debug, accepting changes only after compile, simulation, and regression checks.
FPT26 - FPGA Track
FPGA · Llama 3-8B · AMD Alveo U50 · BF16 · FP32
Collaborated on BRISK, a team FPGA implementation of exact Llama 3-8B attention using single-owner K/V residency on an AMD Alveo U50. The team design placed and routed at 220 MHz with BF16 I/O and FP32 accumulation; measured 1.66x prefill and 2.25x average decode speedup over a same-boundary RTX 5090 baseline.
ADDF Final Project - N16 CNN Accelerator
N16 · CNN Accelerator · DFT · Scan · ATPG · Synthesis · Floorplanning · Placement · CTS · Routing · MMMC STA · DRC/LVS
Integrated scan insertion and compression into an N16 flow; generated and simulated stuck-at ATPG patterns with >99% test coverage and approximately 3% area/power overhead. Executed synthesis, floorplanning, placement, CTS, routing, MMMC STA, scan-chain reorder, DRC/LVS, Voltus analysis, and pre-/post-layout LEC; earned the highest project score in the class.
Caravel/FSIC SoC Verification
RTL Simulation · Gate-Level Simulation · Caravel · FSIC · Falcon Accelerator
Undergraduate Research with Prof. Jiin Lai at National Taiwan University. Performed RTL, pre-layout gate-level, and post-layout dynamic simulations for a T18 Caravel/FSIC SoC integrating a Falcon accelerator; verified FSIC configuration paths and chip-level behavior.
Falcon PQC Accelerator
Vitis HLS · FFT · iFFT · NTT · iNTT · Python · Hardware-Software Co-Design
Special Topic Implementation I & II with Prof. Jiin Lai at National Taiwan University. Contributed to HLS kernel optimization for FFT/iFFT/NTT/iNTT; the team achieved about 200x average kernel speedup over the Python baseline. Supported HW/SW integration and validation of KeyGen, Sign, and Verify APIs; team-level end-to-end speedups reached 5.31x, 2.75x, and 2.3x, respectively.
Education
National Tsing Hua University — M.S., College of Semiconductor Research
National Tsing Hua University — B.S., Electrical Engineering
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