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Research focuses on hardware acceleration for fully homomorphic encryption-based deep learning, including FHE-friendly neural networks, algorithm-hardware co-design, and high-throughput architectures for kernels such as NTT.","fieldKeys":["summary"]},{"id":"skills:0","type":"skills","ordinal":0,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Skills / 技能: AHB-Lite, APB, ASIC Physical Design, Asynchronous FIFO, ATPG, C, C++, Calibre, Clock-Domain Crossing, Deep Learning, Design Compiler, DFT, DMA, DRC/LVS, FFT, FHE, FPGA, Gate-Level Simulation, Hardware Acceleration, iFFT, Innovus, iNTT, LEC, Make, MATLAB, NTT, Place and Route, Power Analysis, PrimeTime, Python, Rail Analysis, RTL Simulation, RTL Verification, Scan, SDRAM, SEC-DED ECC, Static Timing Analysis, Synthesis, SystemVerilog, TetraMax, UART, UVM, Verdi, Verilog, Vitis HLS, Vivado, VLSI, Voltus","fieldKeys":["skills"]},{"id":"discovery:0","type":"discovery","ordinal":0,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Role / 職稱: Semiconductor Research Master's Student. Expertise / 專長: AHB-Lite, APB, ASIC Physical Design, Asynchronous FIFO, ATPG, C, C++, Calibre, Clock-Domain Crossing, Deep Learning, Design Compiler, DFT","fieldKeys":["display_name","headline","skills"]},{"id":"experience:0","type":"experience","ordinal":0,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Experience / 經歷: Teaching Assistant, Integrated Circuit Design Lab at National Tsing Hua University. Sep. 2025 to Dec. 2025. Mentored 75 students in RTL design and debugging; developed a Transformer-model reference design and explained topics including clock gating and synthesis.","fieldKeys":["experiences"]},{"id":"education:0","type":"education","ordinal":0,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Education / 學歷: M.S.. College of Semiconductor Research. National Tsing Hua University","fieldKeys":["educations"]},{"id":"education:1","type":"education","ordinal":1,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Education / 學歷: B.S.. Electrical Engineering. National Tsing Hua University","fieldKeys":["educations"]},{"id":"project:0","type":"project","ordinal":0,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Project / 專案: SiCADA 600 - SoC Design & Verification Course Project. Built with / 使用技術: AHB-Lite, DMA, APB, Clock-Domain Crossing, Asynchronous FIFO, SEC-DED ECC, UVM, SystemVerilog. Integrated a dual-clock AHB-Lite DMA subsystem with packet reception, APB-programmable control, asynchronous FIFO/metadata CDC, and SEC-DED ECC; passed 68 end-to-end packets with 0 scoreboard mismatches. Built course-project UVM testbenches with sequencers, drivers, monitors, scoreboards, and functional coverage. Used instructor-approved GenAI for implementation/debug, accepting changes only after compile, simulation, and regression checks.","fieldKeys":["projects"]},{"id":"project:1","type":"project","ordinal":1,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Project / 專案: FPT26 - FPGA Track. Built with / 使用技術: FPGA, Llama 3-8B, AMD Alveo U50, BF16, FP32. Collaborated on BRISK, a team FPGA implementation of exact Llama 3-8B attention using single-owner K/V residency on an AMD Alveo U50. The team design placed and routed at 220 MHz with BF16 I/O and FP32 accumulation; measured 1.66x prefill and 2.25x average decode speedup over a same-boundary RTX 5090 baseline.","fieldKeys":["projects"]},{"id":"project:2","type":"project","ordinal":2,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Project / 專案: ADDF Final Project - N16 CNN Accelerator. Built with / 使用技術: N16, CNN Accelerator, DFT, Scan, ATPG, Synthesis, Floorplanning, Placement, CTS, Routing, MMMC STA, DRC/LVS. Integrated scan insertion and compression into an N16 flow; generated and simulated stuck-at ATPG patterns with >99% test coverage and approximately 3% area/power overhead. Executed synthesis, floorplanning, placement, CTS, routing, MMMC STA, scan-chain reorder, DRC/LVS, Voltus analysis, and pre-/post-layout LEC; earned the highest project score in the class.","fieldKeys":["projects"]},{"id":"project:3","type":"project","ordinal":3,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Project / 專案: Caravel/FSIC SoC Verification. Built with / 使用技術: RTL Simulation, Gate-Level Simulation, Caravel, FSIC, Falcon Accelerator. Undergraduate Research with Prof. Jiin Lai at National Taiwan University. Performed RTL, pre-layout gate-level, and post-layout dynamic simulations for a T18 Caravel/FSIC SoC integrating a Falcon accelerator; verified FSIC configuration paths and chip-level behavior.","fieldKeys":["projects"]},{"id":"project:4","type":"project","ordinal":4,"locale":"en","text":"Yan-Jhih Wang. Semiconductor Research Master's Student. Project / 專案: Falcon PQC Accelerator. Built with / 使用技術: Vitis HLS, FFT, iFFT, NTT, iNTT, Python, Hardware-Software Co-Design. Special Topic Implementation I & II with Prof. Jiin Lai at National Taiwan University. Contributed to HLS kernel optimization for FFT/iFFT/NTT/iNTT; the team achieved about 200x average kernel speedup over the Python baseline. Supported HW/SW integration and validation of KeyGen, Sign, and Verify APIs; team-level end-to-end speedups reached 5.31x, 2.75x, and 2.3x, respectively.","fieldKeys":["projects"]}]}